TY  - BOOK
AU  - Bhasker,J.
TI  - Verilog HDL synthesis: a practical primer 
SN  - 8178000113 :
U1  - 621.392 
PY  - 2001///
CY  - Hyderabad
PB  - BS Pub.
KW  - Verilog (Computer hardware description language)
KW  - Logic design
KW  - Data processing
KW  - Computer hardware description languages
N1  - Includes bibliographical references and index
ER  -