Hachtel, Gary D. <br/><br/>
Logic synthesis and verification algorithms / 
by Gary D. Hachtel [and] Fabio Somenzi 
 - Boston :  Kluwer Academic Publishers,  c1996 
 - xxxi, 564 p. :  ill. ;  26 cm. 
<br/><br/><label>ISBN: </label> F180.00 
<br/><br/><label>Subjects--Topical Terms: </label><br/>Integrated circuits--Very large scale integration--Design--Data processing<br/>Logic design--Data processing<br/>Integrated circuits--Verification<br/>Computer-aided design
<br/><br/><label>Dewey Class. No.: </label>005.1